1. Field of the Invention
The present invention generally relates to a semiconductor device and the manufacturing method thereof, and more particularly, to a stacked capacitor structure and the manufacturing method thereof.
2. Description of Related Art
A dynamic random access memory (DRAM) is an integrate circuit device (IC device) broadly employed in various applications. Along with the developments of industries, a demand on a DRAM with a larger storage capacity is increasing. The memory unit in a DRAM is composed of metal oxide semiconductor transistors (MOS transistors) and capacitors electrically connected to each other. The capacitor herein is mainly used to store charges representing the data to be stored, and high capacitance is the key to prevent the stored data from likely being lost. The way to increase the charge-storing capacity of a capacitor is to increase the dielectric coefficient of the dielectric material and reduce the thickness of the dielectric material, plus increasing the surface area of the capacitor. However, in the movement of the semiconductor technology towards sub-micron and deep sub-micron manufacturing level, the traditional capacitor is out of date for the semiconductor industry today. Therefore, the relevant developers are investigating a new dielectric material with a higher dielectric coefficient and a capacitor with a larger surface area so as to increase the capacitance of the capacitor.
In order to further advance the integration of a DRAM, a miniaturization process is absolutely required, where the section area per unit of capacitance and the space between the two electrodes of capacitor are made less and less. In such a limited space, a capacitor is able to provide an adequate capacitance to remain a satisfied signal intensity. Accordingly, the DRAM design needs to focus on the capacitor structure and the layout closely affecting the capacitance thereof. In addition, the DRAM process needs to be simplified so as to increase the production yield and reduce the cost for the DRAM manufacturer.
A conventional planar type capacitor is implemented by a two-dimension (2-D) layout, which occupies a considerable area of the semiconductor substrate for storing charges and thus unsuitable for a highly-integrated design. In contrast, a highly-integrated DRAM is implemented by employing three-dimension (3-D) capacitors, such as stacked capacitors or trench capacitors. In fact, for a memory device with higher integration, the conventional simple 3-D capacitor structure becomes even ineffective; and accordingly, a new design direction which focuses on increasing the surface area of the capacitors employed by a DRAM within a limited substrate area was proposed.
In addition, to effectively increase capacitance, it is preferred to adopt a cylindrical capacitor with a larger total surface area of the inner-and-outer sidewalls and give up the traditional cup-capacitor; although the cup-shape capacitor is more stable. However, the above-mentioned capacitor structure has a large aspect ratio of height over width for obtaining a large surface area, which makes the capacitor weaker in strength and structural instability, and the unstable structure increases the risk of collapse. When the capacitor is collapsed, a twin-bit failure occurs, which can be encountered, for example, in a 90 nm process. In the 90 nm process, a twin-bit failure occurs probably due to the unstable capacitor structure. There are two solutions for the above-mentioned problem: improving the space design of the capacitor structure in active manner or adding supporting structures between the capacitors in the manufacturing process to prevent the capacitors from collapse in passive manner.
A number of US patents involve the above-mentioned supporting structures. The U.S. Pat. No. 7,126,180 provides such a design that a ring-shape/bowl-shape stabling member is disposed at the outer-side of a capacitor, having a upper-wide and lower-narrow figure and fixed near the top portion of the lower electrode of the capacitor, so that the employed stabling members between the capacitors are connected to each other. The US patent application No. 20050161720 provides a solution that a stabling member having a protruding structure is disposed outside the main capacitor structure, and the stabling member with the adjacent connecting member together forms an H-shape layout. The US patent application No. 20050253179 provides a solution that a ring-shape stabling member is embedded in a ring-shape trench and perpendicular to the lower electrode plate of a capacitor. The U.S. Pat. No. 7,247,537 provides a solution that stabling members are respectively located near the top of the lower electrode of a capacitor, and connected to each other. The US patent application No. 20050040448 provides a solution structure that the upper portion of an employed stabling member is inwardly bent. The US patent application No. 20060211178 provides a solution that the employed stabling member is located around the round disc of the lower electrode of a capacitor and connecting members are employed between the lower electrodes.